OFDM SDR Radio front end

Task:

To design a circuit that fulfills the strict jitter requirements of a fast OFDM radio front end.

Challenges:

• Fast signals that require impedance controlled routing
• Extremely low Jitter requirements (200 fs)
• Clean power
• Clear board structure to isolate noise sources from vulnerable circuits

Solution:

A carefully structured power regulator design with low noise DC/DC converters which provide an intermediate supply which is then regulated by low noise LDOs to the final voltage ensure the best possible power quality with reasonable conversion losses.

A carefully planned PCB layout with clearly defined functional areas, ground plane management and meticulously executed bypassing and filtering

Technologies used:

Altium Designer, ICD Stackup Planner, years of experience, and some luck all added up to a first pass success with minimal revision requirements to achieve a production-ready PCB.